The programming model should also abstract away machine dependent hardware details. ![]() Such a model allows the programmer to express different types and granularities of parallelism as well as computation characteristics of importance in the addressed class of applications. Automated parallelization, optimization and mapping to a many core processor benefits from the use of a concurrent programming model as the starting point. We argue for code mapping strategies based on predicted execution performance, which can be used in an auto-tuning feedback loop or to guide manual tuning directed by the programmer. In particular, the focus is put on how to provide a means for tunable strategies for mapping of task graphs on array structured distributed memory many cores, with respect to given application constraints. Further, we outline a tool flow based on methods and analysis techniques for automated, multi-objective mapping of such applications on distributed memory many core processors. ![]() We propose building two-level hierarchical computer architectures for this domain of applications. This thesis addresses the development of high-performance digital signal processing systems relying on many core technology. Thus the requirements are of both functional and non-functional nature. The term embedded further implies requirements on physical size and power efficiency. The term high-performance translates to large amounts of data and computations per time unit. Advanced digital signal processing systems require specialized high-performance embedded computer architectures.
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